In modem SoC systems (SoC: System on Chip), asynchronous clock signals are provided with a digital clock divider. In such cases, a first clock signal with a relatively high frequency is applied to the digital clock divider, and a second clock signal with a lower frequency relative to the first frequency is generated from the first high frequency and output by the clock divider by means of an applied control signal. The frequency will in this case vary from one interval to another, depending on the divider factor, which is applied by means of the control signal. Normally, the resulting jitter is in the range of allowable jitter for digital interfaces.
Clock dividers normally use a so called digitally controlled oscillator (DCO). In such an arrangement, each input clock triggers an addition in an accumulator using a defined offset. The accumulator allows an overflow, so that the most significant bit (MSB/Most Significant Bit) represents a clock signal with a lower rate, which is proportional to the offset.
A disadvantage of such an arrangement is that an addition must take place at a very high input rate, which results in a high current consumption of the clock divider. An additional disadvantage is that the programmable output frequencies are uniformly distributed throughout the range between zero and the input frequency. As a consequence, a large bit width of the accumulator is required to achieve an adequate frequency resolution. The large bit width of the accumulator also has a detrimental influence on current consumption.
Moreover, yet another disadvantage is that the jitter is comparable to that of a first order noise shaper (Noise Shaper), whereby low frequency disturbance lines can occur in the spectrum of the output clock signal. Such disturbance lines can lead to problems with the recovery of the clock signal, which has to be provided without a jitter. Alternatively, such disturbance lines can lead to whistling sounds in the case of an application in the audio area.